As a wiring board on which semiconductor components such as LSIs, ICs, etc. are mounted or in which various thick printed elements are built, a multilayer wiring board in which resin dielectric layers and metal conductor layers are laminated alternately on opposite surfaces of a plate core formed from a glass reinforced resin or the like has been used. The metal conductor layers contain a wiring portion for signal transmission. In recent years, boards used in high clock frequency computer equipment, optical communication equipment, etc., have supported signal frequencies in a high frequency band beyond 1 GHz. In the wiring portion of such a board, a high frequency shield line such as a strip line or a microstrip line has been used.
Matching characteristic impedance with a rated value (50 Ω) is performed in a well-worn manner for enhancing the signal transmission efficiency in the wiring portion in the multilayer wiring board. The strip line or microstrip line can be designed to have a transmission line structure with rated characteristic impedance on the basis of a distributed parameter circuit theory using an interval between each surface conductor (ground layer or power supply layer) and the line opposite to each other, a line width, a dielectric constant of dielectric between the surface conductor and the line, etc. as parameters.
A signal transmission path in the multilayer wiring board is formed to range from a pad (e.g. a solder land for making a flip chip connection with a semiconductor component) formed on a first main surface side of the plate core to a pad (e.g. a BGA or PGA pad for connecting with a mother board) formed on a second main surface side of the plate core. In this case, as described above, desired characteristic impedance of the conductor line portion drawn around in the conductor layer can be achieved comparatively easily by a well-known theory design technique in accordance with the form of the high frequency shield line. However, in consideration of installation of the board into a real product, the characteristic impedance of the whole multilayer wiring board, that is, the whole signal transmission path between the pads is required to be matched with the rated value.
In addition to the line portion having theoretically rated characteristic impedance (hereinafter referred to as “standard impedance portion”) such as a strip line or a microstrip line, many portions having characteristic impedance other than the rated value (hereinafter referred to as “nonstandard impedance portions”) are mixed on the signal transmission path. Examples of the nonstandard impedance portions include via conductors, through-hole conductor portions penetrating the plate core, pads disposed on the surfaces of the board, etc. Each of the nonstandard impedance portions is a factor to cause impedance mismatching. In this case, it is conceived that impedance matching can be attained by changing the line width of the strip line or the microstrip line constituting the standard impedance portion, a thickness of each dielectric layer, etc. This is regarded as a solution in which the problem caused by the nonstandard impedance portions is loaded on the so-called standard impedance portion side. It is highly likely that even the design of the whole board will be affected by the solution. If possible, it is desired that such a solution is not used.
The nonstandard impedance portion, for example, a via or a through-hole conductor, does not include a surface conductor (for ground or power supply) which has to be essentially included in any standard impedance portion. Therefore, there is a tendency that the nonstandard impedance portion is lower in capacitance but higher in reactance than the standard impedance portion. On the other hand, high parasitic capacitance is formed between each conductor pad and a surface conductor disposed around the conductor pad or disposed oppositely to the conductor pad through a dielectric layer. Therefore, there is a tendency that the reactance is decreased conversely. When coupling is formed between the capacitance and inductance, there appears a zero point or an extreme in the frequency characteristic of the impedance, having significant influence on impedance matching in a desired frequency band.
For example, according to Japanese Patent Laid-Open No. 2001-160598, a method for achieving impedance matching in a board including an electrode pad has been proposed as follows. That is, a condition 0<d≦w is set in which a diameter of an electrode pad is w and an in-plane distance between an inner edge of a via opening and an outer edge of the electrode pad is d, the via opening being formed in a position just under the electrode pad in surface conductor layers opposite to each other with a dielectric layer interposed therebetween. In this manner, parasitic capacitance formed between the electrode pad and each of the surface conductor layers is reduced on a large scale, so that impedance mismatching due to formation of the electrode pad can be cancelled.